Please use this identifier to cite or link to this item: http://hdl.handle.net/2381/1950
Title: A high speed reconfigurable firewall based on parameterizable FPGA-based content addressable memories
Authors: McEwan, A. A.
Saul, J.
First Published: 2001
Citation: Journal of Supercomputing, 2001, 19 (1), pp.93-103
Abstract: A technique for implementing a Content Addressable Memory (CAM) on an FPGA is described. The CAM is highly parameterizable, allowing varying word widths, memory depths and operations to be implemented depending upon the requirements of the target application. The application of the CAM is then demonstrated by using it in the core of a network firewall application, where it is used in a pipeline IP packet detection algorithm. The firewall application is particularly useful in demonstrating the application potential of the CAM as the packet detection algorithm can be dynamically reconfigured to react to different criteria simply by altering the contents of the CAM. The result is a complete system on a chip.
DOI Link: 10.1023/A:1011140512041
ISSN: 0920-8542
Links: http://link.springer.com/article/10.1023%2FA%3A1011140512041
http://hdl.handle.net/2381/1950
Type: Article
Appears in Collections:Published Articles, Dept. of Engineering

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