Please use this identifier to cite or link to this item: http://hdl.handle.net/2381/1965
Title: Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling
Authors: Phatrapornnant. T.
Pont, Michael J.
First Published: 2006
Citation: IEEE Transactions on Computers, 2006, 55 (2), pp.113-124
Abstract: We have previously demonstrated that use of an appropriate dynamic voltage scaling (DVS) algorithm can lead to a substantial reduction in CPU power consumption in systems employing a time-triggered cooperative (TTC) scheduler. In this paper, we consider the impact that the use of DVS has on the levels of both clock and task jitter in TTC applications. We go on to describe a modified DVS algorithm (TTC-jDVS) which can be used where low jitter is an important design consideration. We then demonstrate the effectiveness of the modified algorithm on a data set made up of artificial tasks and in a realistic case study.
DOI Link: 10.1109/TC.2006.29
ISSN: 0018-9340
Links: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1566573
http://hdl.handle.net/2381/1965
Type: Article
Appears in Collections:Published Articles, Dept. of Engineering

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