Please use this identifier to cite or link to this item: http://hdl.handle.net/2381/1965
Full metadata record
DC FieldValueLanguage
dc.contributor.authorPhatrapornnant. T.en_GB
dc.contributor.authorPont, Michael J.en_GB
dc.date.accessioned2009-12-08T16:16:59Z-
dc.date.available2009-12-08T16:16:59Z-
dc.date.issued2006en_GB
dc.identifier.citationIEEE Transactions on Computers, 2006, 55 (2), pp.113-124en_GB
dc.identifier.issn0018-9340en_GB
dc.identifier.urihttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1566573en_GB
dc.identifier.urihttp://hdl.handle.net/2381/1965-
dc.description.abstractWe have previously demonstrated that use of an appropriate dynamic voltage scaling (DVS) algorithm can lead to a substantial reduction in CPU power consumption in systems employing a time-triggered cooperative (TTC) scheduler. In this paper, we consider the impact that the use of DVS has on the levels of both clock and task jitter in TTC applications. We go on to describe a modified DVS algorithm (TTC-jDVS) which can be used where low jitter is an important design consideration. We then demonstrate the effectiveness of the modified algorithm on a data set made up of artificial tasks and in a realistic case study.-
dc.formatMetadataen_GB
dc.language.isoenen_GB
dc.titleReducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scalingen_GB
dc.typeArticleen_GB
dc.identifier.doi10.1109/TC.2006.29-
dc.relation.raeRAE 2007-
Appears in Collections:Published Articles, Dept. of Engineering

Files in This Item:
There are no files associated with this item.


Items in LRA are protected by copyright, with all rights reserved, unless otherwise indicated.