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dc.contributor.authorPhatrapornnant. T.en_GB
dc.contributor.authorPont, Michael J.en_GB
dc.identifier.citationIEEE Transactions on Computers, 2006, 55 (2), pp.113-124en_GB
dc.description.abstractWe have previously demonstrated that use of an appropriate dynamic voltage scaling (DVS) algorithm can lead to a substantial reduction in CPU power consumption in systems employing a time-triggered cooperative (TTC) scheduler. In this paper, we consider the impact that the use of DVS has on the levels of both clock and task jitter in TTC applications. We go on to describe a modified DVS algorithm (TTC-jDVS) which can be used where low jitter is an important design consideration. We then demonstrate the effectiveness of the modified algorithm on a data set made up of artificial tasks and in a realistic case study.-
dc.titleReducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scalingen_GB
dc.relation.raeRAE 2007-
Appears in Collections:Published Articles, Dept. of Engineering

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