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Title: Monitoring and designing predictable time-triggered software architecture for real-time embedded applications
Authors: Chan, Kam Leung
Supervisors: Pont, Michael
McEwan, Alistair
Award date: 1-Oct-2012
Presented at: University of Leicester
Abstract: Modern industrial applications often employ embedded processors – programmed with dedicated software – to perform some tasks in real time. In many such designs, the software running on the processor is developed according to rigorous industry standards. Even with such state-of-the art designs, problems can occur “in the field” due to unforeseen circumstances – such as electromagnetic interference – that could undermine the underlying assumptions made at design time. It therefore remains essential to monitor the system at run-time, in order to detect any deviations from the required system behaviour. However, monitoring embedded systems is a far from trivial process, not least because such systems are becoming increasingly complex. Also, variations in task execution times are likely to occur, and can have negative impacts on system predictability particularly in the presence of jitter-sensitive tasks. In addition, it is rarely possible (or cost-effective) to add precise monitoring capabilities to a system which has not been developed from the outset with such requirements in mind. The work described in this thesis seeks to address these issues by introducing and evaluating a “predictable time-triggered” (pTT) framework that combines: a pTT scheduling algorithm and a hardware-based pTT monitor. A novel jitter-reduction technique in a pTT algorithm allows jitter-sensitive tasks to be executed in constant periods without the need to re-compute the entire task schedule. The studies reported in this thesis show that, with existing jitter-reduction methodologies, a pTT algorithm can provide extremely predictable temporal behaviour. The studies also show that the novel low-cost pTT monitor – that operates by monitoring fluctuations in the processor power consumption through a simple hardware interface – adds an additional level of safety by allowing run-time errors to be detected at a time resolution of microseconds. These findings provide sufficient evidence that the pTT framework could be an appropriate model for safety-critical system design.
Type: Thesis
Level: Doctoral
Qualification: PhD
Rights: Copyright © the author. All rights reserved.
Appears in Collections:Theses, Dept. of Engineering
Leicester Theses

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