Please use this identifier to cite or link to this item: http://hdl.handle.net/2381/3752
Title: Algorithms for Hardware Caches and TLB.
Authors: Rahman, Naila
First Published: 2003
Citation: Algorithms for memory hierarchies : advanced lectures / Ulrich Meyer, Peter Sanders, Jop Sibeyn (eds.), pp. 171-192. Series: Lecture notes in computer science ; 2625. Published by Springer, 2003.
Abstract: Over the last 20 years or so CPU clock rates have grown explosively, and CPUs with clock rates exceeding 2 GHz are now available in the mass market. Unfortunately, the speed of main memory has not increased as rapidly: today’s main memory typically has a latency of about 60 ns. This implies that the cost of accessing main memory can be 120 times greater than the cost of performing an operation on data which are in the CPU’s registers. Since the driving force behind CPU technology is speed and that behind memory technology is storage capacity, this trend is likely to continue. Researchers have long been aware of the importance of reducing the number of accesses to main memory in order to avoid having the CPU wait for data.
DOI Link: 10.1007/3-540-36574-5_8
ISSN: 0302-9743
ISBN: 3540008837
Links: http://link.springer.com/chapter/10.1007%2F3-540-36574-5_8
http://hdl.handle.net/2381/3752
Type: Book chapter
Appears in Collections:Books & Book Chapters, Dept. of Computer Science

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