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Title: Reducing the Concretization Effort in FSM-Based Testing of Software Product Lines
Authors: Fragal, Vanderson Hafemann
Simao, Adenilso
Endo, André Takeshi
Mousavi, Mohammad Reza
First Published: 13-Apr-2017
Presented at: IEEE International Conference on Software Testing, Verification and Validation Workshops (ICSTW)
Start Date: 13-Mar-2017
End Date: 17-Mar-2017
Publisher: IEEE
Citation: Proceedings of the 10th IEEE International Conference on Software Testing, Verification and Validation Workshops, ICSTW 2017, 2017, pp. 329-336
Abstract: To test a Software Product Line (SPL), the test artifacts and the techniques must be extended to support variability. In general, when new SPL products are developed, more tests are generated to cover new or modified features. A dominant source of extra effort for such tests is the concretization of newly generated tests. Thus, minimizing the amount of new nonconcretized tests required to perform conformance testing on new products reduces the overall test effort. In this paper, we propose a test reuse strategy for conformance testing of SPL products that aims at reducing test effort. We use incremental test generation methods based on finite state machines (FSMs) to maximize test reuse. We combine these methods with a selection algorithm used to identify non-redundant concretized tests. We illustrate our strategy using examples and a case study with an embedded mobile SPL. The results indicate that our strategy can save up to 36% of test effort in comparison to current test reuse strategies for the same fault detection capability.
DOI Link: 10.1109/ICSTW.2017.61
ISBN: 978-1-5090-6676-6
Version: Post-print
Type: Conference Paper
Rights: Copyright © 2017, IEEE. Deposited with reference to the publisher’s open access archiving policy.
Appears in Collections:Conference Papers & Presentations, Dept. of Computer Science

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