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Title: Extending fireeRTOS to Support Dynamic and Distributed Mapping in Multiprocessor Systems
Authors: Abich, G.
Mandelli, M. G.
Rosa, F. R.
Moraes, F.
Ost, L.
Reis, R.
First Published: 6-Feb-2017
Presented at: 23rd IEEE International Conference on Electronics, Circuits and Systems (ICECS), Monte Carlo, Monaco
Start Date: 11-Dec-2016
End Date: 14-Dec-2016
Publisher: IEEE
Citation: 23rd IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2016, pp. 712-715 (4)
Abstract: Multiprocessor embedded architectures are driven by power wall, performance scalability and reliability challenges. Aiming to effectively scale up system performance while meeting energy-efficiency constraints, multiprocessor architectures are dividing application workloads among multiple threads/tasks [1]. The way such tasks are mapped onto the processing elements (PEs) has a significant impact on system performance, energy-efficiency and reliability [2]. With 1000-processors platforms already available in the embedded community [3], grows the demand for distributed dynamic mapping techniques capable of allocating multi application tasks efficiently. Mapping techniques have been investigated over the last years, considering different optimization goals (e.g. energy consumption, latency, etc). Most of such mapping techniques are customized implementations, which are developed based on an in-house OS. While providing optimized and efficient means for the mapping techniques, in-house OS based implementations usually are processor-dependent. With the advance of embedded processors, at some point, it will become necessary to port such in-house implementations to a more performant or energy-efficient processor architecture. Underlying porting process is likely to lead to extra design, re-validation and, consequentially a hidden cost that may well be quite high. The goal of this work is to provide a version of FreeRTOS [4] that supports a set of distributed and dynamic task mapping heuristics, which can be easily employed by almost thirty different processor architectures. Due to the non-intrusive and flexible implementation, promoted extensions provide an efficient means not only to use and extend available heuristics but also to integrate new ones.
DOI Link: 10.1109/ICECS.2016.7841301
ISSN: 978-1-5090-6112-9
Version: Post-print
Status: Peer-reviewed
Type: Conference Paper
Rights: Copyright © 2017, IEEE. Deposited with reference to the publisher’s open access archiving policy. (
Appears in Collections:Conference Papers & Presentations, Dept. of Engineering

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